PAR: Place And Route Diamond Version 2.1.1.104.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation,  All rights reserved.
Tue Jun 25 17:33:38 2013

C:/lscc/diamond/2.1/ispfpga\bin\nt\par -f single_led_single_led.p2t
single_led_single_led_map.ncd single_led_single_led.dir
single_led_single_led.prf


Preference file: single_led_single_led.prf.

Cost Table Summary
Level/      Number      Worst       Timing      Run         NCD
Cost [ncd]  Unrouted    Slack       Score       Time        Status
----------  --------    -----       --------    -----       ------
5_1   *     0           -           -           08          Complete        


* : Design saved.

Total (real) run time for 1-seed: 8 secs 

par done!

Lattice Place and Route Report for Design "single_led_single_led_map.ncd"
Tue Jun 25 17:33:38 2013


Best Par Run
PAR: Place And Route Diamond Version 2.1.1.104.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF single_led_single_led_map.ncd single_led_single_led.dir/5_1.ncd single_led_single_led.prf
Preference file: single_led_single_led.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file single_led_single_led_map.ncd.
Design name: blinker
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP144
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/2.1/ispfpga.
Package Status:                     Final          Version 1.39
Performance Hardware Data Status:   Final          Version 23.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)       2/108           1% used
                      2/108           1% bonded

   SLICE             14/640           2% used



Number of Signals: 66
Number of Connections: 80

Pin Constraint Summary:
   2 out of 2 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    clk_c (driver: clk, clk load #: 14)


No signal is selected as secondary clock.

No signal is selected as Global Set/Reset.
Starting Placer Phase 0.

Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
..................
Placer score = 276.
Finished Placer Phase 1.  REAL time: 7 secs 

Starting Placer Phase 2.
.
Placer score =  276
Finished Placer Phase 2.  REAL time: 7 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 1 out of 8 (12%)
  PLL        : 0 out of 1 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clk_c" from comp "clk" on CLK_PIN site "128 (PT12A)", clk load = 14

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 0 out of 8 (0%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   2 out of 108 (1.9%) PIO sites used.
   2 out of 108 (1.9%) bonded PIO sites used.
   Number of PIO comps: 2; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+---------------+------------+-----------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref |
+----------+---------------+------------+-----------+
| 0        | 2 / 28 (  7%) | 2.5V       | -         |
| 1        | 0 / 26 (  0%) | -          | -         |
| 2        | 0 / 28 (  0%) | -          | -         |
| 3        | 0 / 26 (  0%) | -          | -         |
+----------+---------------+------------+-----------+

Total placer CPU time: 7 secs 

Dumping design to file single_led_single_led.dir/5_1.ncd.


-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.  
-----------------------------------------------------------------

0 connections routed; 80 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 8 secs 

Start NBR router at 17:33:46 06/25/13

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design. Thanks.                                       
*****************************************************************

Start NBR special constraint process at 17:33:46 06/25/13

Start NBR section for initial routing
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 8 secs 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 8 secs 

Start NBR section for re-routing
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 8 secs 

Start NBR section for post-routing

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack : 
  Timing score : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.


Total CPU time 8 secs 
Total REAL time: 8 secs 
Completely routed.
End of route.  80 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file single_led_single_led.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 

Total CPU  time to completion: 8 secs 
Total REAL time to completion: 8 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation,  All rights reserved.